1. Field of the Invention
The present invention generally relates to input/output control in multi-processor data processing systems employing shared resources and, more particularly, to a device access management method which is effective to prevent device lockout due to fast channel input/output turn-around time of new, faster processors which are connected to the data processing system.
2. Description of the Prior Art
With the introduction of newer and faster processors, a phenomenon described as device lockout has been observed when, for example, a direct access storage device (DASD) subsystem controller is attached to these processors in a shared DASD environment. When more than one processor requires access to the same device, the controller will accept an input/output operation from one and signal busy to the other(s). This usually indicates that when the device becomes free, the controller will then signal the waiting processor so that the pending input/output operation can be initiated.
The controller requires a certain amount of time in order to do housekeeping after the end of an input/output operation. This housekeeping must be completed prior to signaling a waiting processor that the requested device is now available for an input/output operation. At the same time, the channel requires an amount of time to process the results of an input/output operation before it can initiate a new operation on a given device. If the time that the channel requires to process the current operation and start a new one is greater than what the device controller requires for clean up, then the controller is allowed enough time to signal other processors that the device is now free.
A problem can arise if the channel turn-around time is less than the controller end-of-chain clean up time. This problem occurs because the controller will allow selection even though the clean up activity has not been completed and another waiting processor has not been signalled. In other words, the processor just completing an operation can initiate new input/output operations for as long as there are queued operations pending for any device under the control of that controller. The results are that the other processors are denied access to that device for long periods. This problem can grow in severity since the queues will increase for the processors waiting for the device.
The device lockout problem is related to the speed of the processor and its associated channels only to the point where the channel turn-around time becomes less than the controller's turn around or housekeeping time. Once this threshold value has been breached, a given processor may hold off an even faster processor which previously had been given a device busy. In this condition, a processor may have exclusive use of a device or a controller for as long as is necessary to process pending input/output requests.
This condition can and does occur since the controller is never allowed to raise request-in to signal other processors when the device or controller is free. Since the current processor already knows the device or path could be free and there are pending input/output operations in its queue, subsequent input/output operations will be initiated until the queue is exhausted. Unfortunately, while all of this is going on, queued operations build up for that controller or device or other devices under that controller on other processors.
In some environments, the problem of device or controller lockout can be so severe as to lead to a system outage. An example where this might occur is in an airline reservation system. However, even before a system outage occurs, other problems become manifest. Again, in the airline reservation system environment, if records are not available to an application program for long periods of time, the records tend to age and become invalid. This can result in over booking of reservations and even booking on discontinued flights.
As mentioned, the subject invention relates to multi-processor data processing systems employing shared resources such as DASDs. Such systems are known in the prior art as exemplified by U.S. Pat. No. 4,096,567 to Millard et al. and U.S. Pat. No. 4,228,496 to Katzman et al. Neither of these patents, however, recognize the problem solved by this invention. U.S. Pat. No. 4,004,277 to Gavril discloses a switching system for permitting a secondary computer to share the peripheral equipment of a main computer. The Gavril system does not allow equal access to the peripheral equipment. Bacot et al., in U.S. Pat. No. 4,426,681, describe a data processing system in which conflicts raised by multiple accesses to the same cache memory by several processors are resolved. Basically, this system operates to raise a busy status to other processors when the cache is accessed by one processor.
Also known in the prior art are various input/output controllers for managing the communications between a central processing unit and several peripheral devices. See for example U.S. Pat. No. 3,725,864 to Clark et al., U.S. Pat. No. 3,938,098 to Garlic, U.S. Pat. No. 4,106,092 to Millers, II, U.S. Pat. No. 4,162,520 to Cook et al., and U.S. Pat. No. 4,313,160 to Kaufman et al. It is known in such input/output controllers to provide a method for resolving the priority of a plurality of input/output devices. One example is described in U.S. Pat. No. 4,271,467 to Holtey. In U.S. Pat. No. 3,949,371 to Pederzini, there is described an input/output system having cyclical scanning of interrupt requests by a plurality of perpherial devices to a central processing unit. A system of hierarchically organized priority levels is combined with cyclical scanning so that no single device may monopolize the central processor.
Examples of DASD controllers are disclosed in U.S. Pat. No. 4,310,882 to Hunter et al. and U.S. Pat. No. 4,499,539 to Vosacek. Both of these patents describe systems for increasing the effectiveness of the DASD units.